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LSM2 Series
Single Output, Non-Isolated
Selectable-Output POL DC/DC Converters
Operation
To use the Sequence pin after power start-up stabilizes, apply a rising external
voltage to the Sequence input. As the voltage rises, the output voltage will
track the Sequence input (gain = 1). The output voltage will stop rising when it
reaches the normal set point for the converter. The Sequence input may option-
ally continue to rise without any effect on the output. Keep the Sequence input
voltage below the converter’s input supply voltage.
Use a similar strategy on power down. The output voltage will stay constant
until the Sequence input falls below the set point.
Any strategy may be used to deliver the power up/down ramps. The circuits
below show simple RC networks but you may also use operational ampli?ers,
D/A converters, etc.
Circuits
The circuits shown in Figures 14 through 16 introduce several concepts when
using these Sequencing controls on Point-of-Load (POL) converters. These
circuits are only for reference and are not intended as ?nal designs ready for
your application. Also, numerous connections are omitted for clarity.
Figure 15 shows a single POL and the same RC network. However, we have
added a FET at Q1 as an up/down control. When V IN power is applied to the
POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased
off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate. Note:
Q1’s gate would typically be controlled from some external digital logic.
Figure 15. Self-Ramping Power Up
If you wish to have a ramped power down (rather than a step down), add a
small resistor in series with Q1’s drain.
Figure 16 shows both a RC ramp on Master POL A and a proportional track-
ing divider (R2 and R3) on POL B. We have also added an optional very small
noise ?lter cap at C2. Figure 16’s circuit corresponds roughly to Figure 11’s
timing for power up.
Figure 14. Wiring for Simultaneous Phasing
Figure 14 shows a basic Master (POL A) and Slave (POL B) connected so the
POL B ramps up identically to POL A as shown in timing diagram, Figure 10. RC
network R1 and C1 charge up at a rate set by the R1-C1 time constant, giving
a roughly linear ramp. As POL A reaches 3.3V OUT (the setpoint of POL B), POL
B will stop rising. POL A then continues rising until it reaches 5V. R1 should be
signi?cantly smaller than the internal bias current resistor from the Sequence
pin. Start with a 20k ?? value. We assume that the critical phase is only on
Figure 16. Proportional Phasing
power up therefore there is no provision for ramped power down.
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